The semiconductor industry has experienced rapid growth due to continuous increase in functionality and speed of integrated circuits for any given cost. This has been enabled primarily by continuous improvements in the integration density of functional circuit blocks, e.g., memory arrays, digital logic gates, differential amplifiers and the like. This increase in density has been achieved by two means: (1) increased planar density due to repeated reductions in minimum feature size and, (2) increased vertical integration achieved by stacking an increasing number of interconnect levels and components. The former allows for a denser placement of electronic components (e.g., transistors) and metal conductors at any given level, whereas the latter allows for placement of components and routing signals and power lines using multiple levels located vertically above each other.
A majority of electronic components are formed in a semiconductor substrate. These, as well as other electronic components, are connected to each other and to external signals and power supplies according to a circuit design to construct an integrated circuit (IC). These connections are achieved by conductive interconnect structures, such as lines and vias that collectively constitute a multilevel interconnect system with its elements formed at multiple discrete levels above the substrate.
Corresponding numerals and symbols in the different figures generally refer to corresponding elements, unless otherwise indicated. The figures are drawn to representatively illustrate relevant aspects of disclosed embodiments and are not necessarily drawn to scale.